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Language modes Verilog/SystemVerilog
SystemVerilog mode
// Literals 1'b0 1'bx 1'bz 16'hDC78 'hdeadbeef 'b0011xxzz 1234 32'd5678 3.4e6 -128.7
// Macro definition `define BUS_WIDTH = 8;
// Module definition module block( input clk, input rst_n, input [`BUS_WIDTH-1:0] data_in, output [`BUS_WIDTH-1:0] data_out );
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin data_out
var editor = CodeMirror.fromTextArea(document.getElementById("code"), { lineNumbers: true, matchBrackets: true, mode: { name: "verilog", noIndentKeywords: ["package"] } });
Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800). Configuration options:
noIndentKeywords - List of keywords which should not cause indentation to increase. E.g. ["package", "module"]. Default: None
MIME types defined: text/x-verilog and text/x-systemverilog .